Cmos imager pixel designs

ABSTRACT

A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.

FIELD OF THE INVENTION

The present invention relates to improved semiconductor imaging devicesand, in particular, to a CMOS imager employing a storage capacitor inthe pixel sensor cell.

BACKGROUND OF THE INVENTION

CMOS imagers have been increasingly used as low cost imaging devices. Afully compatible CMOS sensor technology enabling a higher level ofintegration of an image array with associated processing circuits isbeneficial in many digital imaging applications such as, for example,cameras, scanners, machine vision systems, vehicle navigation systems,video telephones, computer input devices, surveillance systems, autofocus systems and star trackers, among many others.

In a conventional CMOS imager, the active elements of a pixel cellperform the necessary functions of: (1) photon to charge conversion; (2)accumulation of image charge; (3) transfer of charge to a floatingdiffusion node accompanied by charge amplification; (4) resetting thefloating diffusion node to a known state before the transfer of chargeto it; (5) selection of a pixel for readout; and (6) output andamplification of a signal representing pixel charge. Photo charge may beamplified when it moves from the initial charge accumulation region tothe floating diffusion node. The charge at the floating diffusion nodeis typically converted to a pixel output voltage by a source followeroutput transistor. The photosensitive element of a CMOS imager pixel istypically either a depleted p-n junction photodiode or a field induceddepletion region beneath a photogate.

Exemplary CMOS imaging circuits as well as detailed descriptions of thefunctions of various CMOS elements of an imaging circuit are described,for example, in U.S. Pat. No. 6,204,524 to Rhodes, U.S. Pat. No.6,310,366 to Rhodes et al. and U.S. Pat. No. 6,326,652 to Rhodes, thedisclosure of which are incorporated by reference herein.

Since prior CMOS imagers suffer from poor signal to noise ratios andpoor dynamic range as a result of the inability to fully collect andstore the electric charge collected by the photosensitive area, storagecapacitors have been proposed for use in connection with the lightsensitive node of a CMOS pixel sensor cell to improve collected chargestorage. For example, U.S. Pat. No. 6,204,524 to Rhodes describes indetail the formation of planar and trench storage capacitorselectrically connected in parallel to the light sensitive node of a CMOSpixel sensor cell and formed partially over the field oxide region andpartially over the active pixel region.

Applicants of the present invention have discovered that storagecapacitors may also provide useful results when electrically connectedto other light sensitive and/or electrical elements of the pixel sensorcell, such as transistor gates or floating diffusion regions, forexample, to affect the operation and characteristics of such variouslight sensitive and/or electrical elements. Capacitors connected to suchvarious light sensitive and/or electrical elements of the pixel sensorcell help amplify the signal of an imager transistor, increase thestorage capacitance of a photosite, or provide a low noise decouplingcapacitor. Such capacitors may be formed entirely over the active areaof the pixel sensor cell, or entirely over the field oxide area, or overboth the active area and the field oxide area.

SUMMARY OF THE INVENTION

The present invention provides CMOS imagers having storage capacitorselectrically connected to various light sensitive and/or electricalelements of a pixel sensor cell of a CMOS imager, to affect theoperation and characteristics of such various light sensitive and/orelectrical elements, add charge storage capability to the pixel sensorcell, independently set charge amplification, and improve the lag andscalability of pixel cells.

According to one embodiment of the present invention, a charge storagecapacitor is formed electrically connected to a floating diffusionregion of a pixel sensor cell and to an AC ground. The charge storagecapacitor may be formed entirely overlying the field oxide regionisolating a pixel sensor cell, or entirely overlying the active area ofthe imager, or partially over the field oxide area and partially overthe active area.

According to another embodiment of the present invention, a chargestorage capacitor is formed electrically connected to and in parallelwith a gate of a CMOS imager transistor, for example, a charge transfertransistor, to tailor the voltage pulses to the transfer gate and thecharge transfer characteristics of the transistor. The charge storagecapacitor may be formed entirely overlying the field oxide region, orentirely overlying the active area of the pixel sensor cell, orpartially over the field oxide area and partially over the active area.

In yet another embodiment of the present invention, a plurality ofstorage capacitors are formed over a field oxide region isolating apixel sensor cell, and further connected to various light sensitive orelectrical elements of the imager, for example, one storage capacitormay be connected to a floating diffusion region and another storagecapacitor may be connected to a charge collection region. Again, each ofthe charge storage capacitors may be formed entirely overlying the fieldoxide region, or entirely overlying the active area of a pixel sensorcell, or partially over the field oxide area and partially over theactive area.

Other embodiments provide a capacitor at one or more other connectionlocations of a pixel sensor cell, which can be formed entirely over afield oxide area, entirely over an active pixel area, or over a portionof a field oxide area and an active pixel area.

Also provided are methods of forming the CMOS imagers containing chargestorage capacitors formed entirely over a field oxide area, entirelyover an active pixel area, or only over a portion of an active pixelarea.

Additional advantages and features of the present invention will beapparent from the following detailed description and drawings whichillustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a pixel sensor cell fabricated inaccordance with a first embodiment of the present invention.

FIG. 2 is another part schematic part cross-sectional substrate view ofthe pixel sensor cell of FIG. 1.

FIG. 3 is a top planar view of the pixel sensor cell of FIG. 1.

FIG. 4 illustrates a cross-sectional view of a pixel sensor cell ofaccording to an embodiment of the present invention and at an initialstage of processing.

FIG. 5 illustrates a cross-sectional view of the pixel sensor cell ofFIG. 4 at a stage of processing subsequent to that shown in FIG. 4.

FIG. 6 illustrates a cross-sectional view of the pixel sensor cell ofFIG. 4 at a stage of processing subsequent to that shown in FIG. 5.

FIG. 7 illustrates a cross-sectional view of the pixel sensor cell ofFIG. 4 at a stage of processing subsequent to that shown in FIG. 6.

FIG. 8 illustrates a cross-sectional view of the pixel sensor cell ofFIG. 4 at a stage of processing subsequent to that shown in FIG. 7.

FIG. 9 illustrates a cross-sectional view of the pixel sensor cell ofFIG. 4 at a stage of processing subsequent to that shown in FIG. 8.

FIG. 10 illustrates a cross-sectional view of the pixel sensor cell ofFIG. 4 at a stage of processing subsequent to that shown in FIG. 9.

FIG. 11 illustrates a cross-sectional view of a pixel sensor cellfabricated according to another embodiment of the present invention.

FIG. 12 is a schematic diagram of a pixel sensor cell fabricated inaccordance with a second embodiment of the present invention.

FIG. 13 is a top planar view of the pixel sensor cell of FIG. 12.

FIG. 14 is a schematic diagram of a pixel sensor cell fabricated inaccordance with a third embodiment of the present invention.

FIG. 15 is a schematic diagram of a pixel sensor cell fabricated inaccordance with a fourth embodiment of the present invention.

FIG. 16 is a schematic diagram of a pixel sensor cell fabricated inaccordance with a fifth embodiment of the present invention.

FIG. 17 is a schematic diagram of a pixel sensor cell fabricated inaccordance with a sixth embodiment of the present invention.

FIG. 18 is a schematic diagram of a pixel sensor cell fabricated inaccordance with a seventh embodiment of the present invention.

FIG. 19 is an illustration of a processing system utilizing the pixelsensor cells of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

The terms “wafer” and “substrate” are to be understood as asemiconductor-based material including silicon-on-insulator (SOI) orsilicon-on-sapphire (SOS) technology, doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. Furthermore, whenreference is made to a “wafer” or “substrate” in the followingdescription, previous process steps may have been utilized to formregions or junctions in the base semiconductor structure or foundation.In addition, the semiconductor need not be silicon-based, but could bebased on silicon-germanium, germanium, or gallium arsenide.

The term “pixel” refers to a picture element unit cell containing aphotosensor and transistors for converting light radiation to anelectrical signal. For purposes of illustration, a representative pixelis illustrated in the figures and description herein and, typically,fabrication of all pixels in an imager will proceed simultaneously in asimilar fashion.

Referring now to the drawings, where like elements are designated bylike reference numerals, FIGS. 1-10 illustrate a first exemplaryembodiment of the invention. A pixel sensor cell 100 (FIGS. 1-3 and 10)is illustrated having a storage capacitor 199 (FIGS. 1-3 and 10)overlying field oxide region 115 and electrically connected to afloating diffusion region 130 and to AC ground. As explained in moredetail below, the storage capacitor 199 is formed so that it does notblock any light sensitive areas of the imager. In addition and asillustrated in FIG. 3, for example, the storage capacitor 199 is formedoverlying the field oxide region 115 entirely, without blocking thefloating diffusion region 130. However, the storage capacitor 199 may bealso formed entirely over the active area, or only partially over thefield oxide area and partially over the active area, as desired.

It should be noted that, although the invention will be described belowin connection with use in a four-transistor (4T) pixel cell, theinvention also has applicability to all CMOS imagers including but notlimited to a three-transistor (3T) cell, which differs from the 4T cellin the omission of a charge transfer transistor described below.Accordingly, an embodiment showing use of the invention in a 3T pixelcell is also discussed below.

FIGS. 1 and 2 are schematic illustrations of the pixel sensor cell 100showing a four-transistor (4T) cell with the storage capacitor 199electrically connected in parallel with floating diffusion region 130.For a better understanding of the present invention, FIG. 3 illustratesa top view of the pixel sensor cell 100 of FIGS. 5 and 6, depicting thestorage capacitor 199 electrically connected to the floating diffusionregion 130. The four transistors illustrated in FIGS. 1-3 can beidentified by their gates, that is transfer transistor gate 128, resettransistor gate 132, source follower transistor gate 136 and row selecttransistor gate 138. This way, the storage capacitor 199 stores chargeon the floating diffusion 130 and contributes to setting the charge tovoltage amplification of the sensor.

FIG. 2 is a more detailed illustration of the transfer transistor havinggate 128 and of the reset transistor having gate 132 of FIG. 1 as wellas of photodiode 125 electrically connected to gate 128 of the transfertransistor. As shown in FIG. 2, the pixel sensor cell 100 of the firstembodiment is formed in a substrate 116 having a doped layer 120 of afirst conductivity type, which for exemplary purposes is treated as ap-type substrate. A field oxide region 115, which serves to surround andisolate the pixel sensor cell 100, may be formed before the formation ofthe storage capacitor 199. The field oxide region 115 is formed by anyknown technique such as thermal oxidation of the underlying silicon in aLOCOS process, or by etching trenches and filling them with oxide in anSTI process.

The doped layer 120 of FIG. 2 is provided with three doped regions 110,130 and 134, which are doped to a second conductivity type, which forexemplary purposes is treated as n-type. The first doped region 110 isthe doped region that forms the photodiode 125. The second doped region130 is the floating diffusion region, sometimes also referred to as afloating diffusion node. The third doped region 134 is the drain of thereset transistor 131 and is also connected to voltage source Vdd.

The floating diffusion region 130 is connected to the source followertransistor gate 136 by a contact line 144 (FIG. 2) which is typically ametal contact line. The floating diffusion region 130 is also connectedto bottom electrode 108 c of the storage capacitor 199 by contact line146 (FIG. 2), which, as described below, is preferably a metal contactline. In the preferred embodiment, the material forming the sourcefollower gate 136, typically formed of poly, poly/WSix, polyTiSi₂ orpoly/WNx/W, acts as the source follower gate when over active area. Whenthe material forming the source follower gate 136 extends over the fieldoxide area, it acts as the bottom electrode 108 c. Dielectric 158 c,which is typically formed of an oxide such as SiO₂, Al₂O or Ta₂O₅, anitride, or an oxide/nitride combination, overlies the bottom electrode108 c. As described in detail below, top capacitor electrode 168 coverlies the dielectric 158 c and is connected through a contact and ametal line 175 to AC ground, which can be a DC ground or a DC supplyvoltage, Vdd.

The source follower transistor 136 outputs a signal proportional to thecharge accumulated in the floating diffusion region 130 to a readoutcircuit 60 when the row select transistor 138 is turned on. While thesource follower transistor 136 and row select transistor 138 areillustrated in FIG. 2 in circuit form above substrate 120, it should beunderstood that these transistors are typically formed in substrate 120in a similar fashion to transistors 128 and 132, as shown in FIG. 3.

The storage capacitor 199 of the pixel sensor cell 100 of FIGS. 1-3 isfabricated by a process described as follows and illustrated in FIGS.4-10. Referring now to FIG. 4, a substrate 116, which may be any of thetypes of substrates described above, is doped to form a doped substratelayer 120 of a first conductivity type, which for exemplary purposeswill be described as p-type. Any suitable doping process may be used,such as ion implantation. Further, the invention has equal applicationto other semiconductor substrates, for example, silicon-germanium,germanium, silicon-on-insulator, silicon-on-saphire, or gallium-arsenidesubstrates, among others. Also illustrated in FIG. 4 is field oxideregion 115, which surrounds and isolates active area A (FIG. 4) of thelater formed pixel sensor cell 100. The field oxide region 115 may beformed by well-known LOCOS or STI processes.

Referring now to FIG. 5, an insulating layer 117 is formed over thesubstrate 116 and the field oxide region 115 by thermal growth orchemical vapor deposition, or other suitable means. The insulating layer117 may be formed of silicon dioxide, silicon nitride, or other suitableinsulating material, and to a thickness of approximately 2 to 100 nm. Asshown in FIG. 5, the insulating layer 117 completely covers thesubstrate 116.

Subsequent to the formation of the insulating layer 117, a firstconductive layer 108, a dielectric layer 158 and a second conductivelayer 168 are sequentially formed over the insulating layer 117, as alsoillustrated in FIG. 5. The first conductive layer 108, which willsimultaneously form a first or bottom electrode 108 c of the storagecapacitor 199 and a gate of the source follower transistor 136, may beformed of any conductive material. Non-limiting examples of materialsthat may be used to form the first conductive layer 108 are dopedpolycrystalline silicon (referred to herein as polysilicon or poly),poly/WSix, polyTiSi₂, poly/WNx/W, among others. The first conductivelayer may be also formed of doped polycrystalline silicon in combinationwith tungsten nitride (WNx) or tungsten silicon (WSix), or a combinationof tungsten nitride and tungsten in addition to polysilicon. The firstconductive layer 108 may be formed over the insulating layer 117 by CVD,LPCVD, PECVD, MOCVD, sputtering (PVD) or other suitable depositiontechniques.

The dielectric layer 158 (FIG. 5) may be formed over the firstconductive layer 108 by various known methods, such as chemical vapordeposition (CVD), rapid thermal nitridation (RTN) processing, or thelike. The term “dielectric” or “insulator” as used in this applicationshall be understood to mean any solid material that can sustain anelectrical field for use in the capacitor of an integrated circuitdevice containing a capacitor. The dielectric layer 158 may be formed ofany insulating material, for example, oxides such as silicon oxide orTEOS, nitrides such as silicon nitride, ONO, NO (nitride oxide) or ON(oxide nitride), high-k dielectrics such as Ta₂O₅, Al₂O₃ or BST,ferroelectrics, or the like. The preferred dielectric layer is a nitridelayer which can be formed by a CVD method.

The second conductive layer 168, which will form a second electrode 168c of the storage capacitor 199, is patterned and formed over thedielectric layer 158. In addition, the second conductive layer 168 maybe formed of the same or different conductive materials from those usedfor the first conductive layer 108. Non-limiting examples of materialsthat may be used to form the second conductive layer 168 are dopedpolycrystalline silicon (referred to herein as polysilicon or poly),platinum, tungsten, TiN, refractory metals, RuO₂, Ir, IrO₂, Rh, RhO_(x),and alloys, such as Pt—Ru or Pt—Rh. The second conductive layer 168 maybe also formed of poly/WSix, poly/WNx/W or polyTiSi₂. The secondconductive layer 168 may be formed over the dielectric layer 158 by CVD,LPCVD, PECVD, MOCVD, sputtering (PVD) or other suitable depositiontechniques. Preferably, both the first and second conductive layers areformed of doped polysilicon with a nitride dielectric layer 158 formedbetween the two conductive layers 108, 168.

Next, the structure of FIG. 5 is patterned using a first photoresistlayer 167 (FIG. 6) formed over the second conductive layer 168 to athickness of about 1,000 Angstroms to about 20,000 Angstroms. The firstphotoresist layer 167 (FIG. 6) is patterned with a mask (not shown) andthe second conductive layer 168 is etched to obtain a second capacitorelectrode 168 c formed over the field oxide region 115, as illustratedin FIG. 7. Subsequent to the formation of the second capacitor electrode168 c, the first photoresist layer 167 is removed by conventionaltechniques, such as oxygen plasma

An insulating layer 164 is then deposited over the second capacitorelectrode 168 c and the dielectric layer 158, as shown in FIG. 8. Theinsulating layer 164 may be any insulating material, such as siliconoxide, silicon dioxide, silicon nitride, USG, BPSG, PSG or BSG, or thelike.

Referring now to FIG. 9, a second photoresist layer 169 is formed overthe insulating layer 164 to a thickness of about 1,000 Angstroms toabout 20,000 Angstroms. The second photoresist layer 169 (FIG. 9) ispatterned with a mask (not shown) and the insulating layer 164, thedielectric layer 158 and the first conductive layer 108 are etchedthrough the patterned photoresist to simultaneously obtain sourcefollower gate stack 136 and completed storage capacitor 199, as shown inFIG. 10. The gate stack 136 is located over the active area of the pixelcell and the storage capacitor 199 is located over the field oxideregion 115. The gate stack 128 comprises conductive layer 108 g formedpreferably of polysilicon, gate dielectric layer 158 g and insulatinglayer 164. The storage capacitor 199 (FIG. 10) comprises first capacitorelectrode 108 c, dielectric 158 c and the second capacitor electrode 168c. Spacers 112 are then formed on the sides of source follower gatestack 136 and of the capacitor 199. Ion implantations are conducted toset transistor voltages, create conductive diffusions and implant thephotodiode. Insulating oxide 171 (FIG. 10) is then deposited andplanarized.

Holes are then etched and contacts 146, 166 and 166 a (FIG. 10) areformed through the planarized insulating oxide 171. Contacts 146, 166and 166 a are formed by applying a photoresist and a mask (not shown)over the planarized oxide layer 171 so that photolithographic techniquescould define the areas to be etched out to form the holes for thecontacts 146, 166, 166 a to the desired electrical circuit. This etchingmay be done at the same time as the etching for the contact holes forthe photogate and reset gate, as described below. The contacts 146, 166,166 a may be filled by depositing therein a conductive material, such asdoped polysilicon, or a metal such as titanium/titanium nitride/tungstenor TiSi₂/TiN/W. As set forth above, the storage capacitor 199 may beformed over any field oxide region of the pixel cell 100.

After the patterning of the storage capacitor 199 and of the gate stack136 of the source follower transistor, gate stack 132 (FIG. 2) of thereset transistor and gate stack 138 of the row select transistor are nowformed. Although, for simplicity, the above embodiment has beendescribed with reference to the formation of the gate stack 136 and theformation of the storage capacitor 199, the invention is not limited tothis embodiment. Accordingly, the present invention also contemplatesthe formation of the storage capacitor 199, and all transistor gates128, 132, 136 and 138 in the array and all necessary elements in theperiphery support circuits.

The processing steps for the fabrication of the reset transistor gate132, transfer transistor gate 128 and photodiode 125 will not bedescribed in detail below, as they are known in the art. Insulatingsidewall spacers 112 (FIG. 2) are also formed on the sides of all gatestacks 128, 132, 136, 138 and the capacitor stack 199. These sidewallsmay be formed of, for example, silicon dioxide, silicon nitride, or ONO.While these gate stacks may be formed before or after the process of thephotodiode 125, for exemplary purposes and for convenience thephotodiode formation has been described as occurring after transistorgate stack formation.

After the formation of the insulating sidewall spacers 112, dopedregions 110, 130 and 134 are then formed in the doped layer 120. Anysuitable doping process may be used, such as ion implantation. A resistand mask (not shown) are used to shield areas of the layer 120 that arenot to be doped. Three doped regions are formed in this step: dopedregion 110 which serves as the photodiode area; doped region 130 whichis floating diffusion region 130 (which connects to the storagecapacitor 199 by contact 146 and to the source follower transistor 136by metal 144 as shown in FIGS. 1-2); and doped region 134 which is adrain region.

As noted earlier, the doped regions 110, 130 and 134 are doped to asecond conductivity type, which for exemplary purposes will beconsidered to be n-type. Several masks may be used to implant theregions 110, 130 and 134 to the same or different doping concentrations.Preferably, the doped regions 110, 130 and 134 are heavily n-doped witharsenic, antimony or phosphorous at a dopant concentration level of fromabout 1×10¹⁵ ions/cm² to about 1×10⁶ ions/cm². Preferably, the dopedregion 110 is a lightly n-type doped region of phosphorous at a dopantconcentration of 1×10¹² ions/cm² to about 1×10¹⁴ ions/cm².

The photosensor cell 100 is essentially complete at this stage, andconventional processing methods may now be used to form wiring toconnect gate lines and other connections in the pixel cell. Accordingly,the entire surface of the substrate 116 is metallized to providecontacts to the floating diffusion, reset gate, transfer gate, Vdd andcapacitor. Conventional multiple layers of conductors and insulators mayalso be used to interconnect the photosensor cell structures.

It should be understood that fabrication of the FIG. 1 structure is notlimited to the methods described with reference to the attached figures.For example, the doped regions 110, 130 and 134 may be formed in thedoped layer 120 before the gates 128 and 132 are formed over thesubstrate. Additionally, the gates 128, 132, 136 and 138 may be formedbefore the storage capacitor 199.

In addition, although the above embodiment was described with referenceto the formation of the reset transistor 132, transfer gate transistor128, and row select transistor 138 subsequent to the formation of thestorage capacitor 199, it must be understood that the invention alsocontemplates the formation of these transistors prior to the formationof the storage capacitor 199.

Although the above embodiment was described with reference to theformation of the storage capacitor 199 entirely overlying the fieldoxide region 115, the invention also contemplates the formation of astorage capacitor formed entirely overlying an active area of a pixelsensor cell. For example, FIG. 11 illustrates storage capacitor 199 aformed entirely over the active area A of the pixel sensor cell 100.

The structure of a pixel cell 200 of a second embodiment of the presentinvention is illustrated with reference to FIGS. 12-13. It should beunderstood that similar reference numbers correspond to similar elementsas previously described with reference to FIGS. 1-11. The structure ofFIG. 12 differs from the above-described embodiment in that storagecapacitor 299 is formed in contact with the photodiode region 125 or110, and not with the floating diffusion region 130, as in the previousembodiment.

The processing of the second embodiment is similar to the processingdescribed above with reference to FIGS. 4-11, except that metal contact246 (FIG. 13) connects an electrode of the storage capacitor 299 to thephotodiode region 110 and not to the floating diffusion region 130, asin the above-described embodiment. Again, the storage capacitor 299 maybe formed entirely or only partially over the field oxide region 115, aswell as entirely or only partially over the active area of the pixelsensor cell. If the storage capacitor 299 is formed entirely over thefield oxide region 115, the advantage is that the storage capacitor 299improves the charge storage capacity of the imager without reducing thesize of the photosensitive area.

FIG. 14 illustrates yet another embodiment of the present inventionaccording to which two different storage capacitors are connected to twodifferent elements of pixel sensor cell 300. For example, FIG. 14depicts storage capacitor 399 a, which is connected to the photodiode125, and storage capacitor 399 b, which is connected to the floatingdiffusion region 130. Both storage capacitors 399 a, 399 b of pixelsensor cell 300 (FIG. 14) may be formed totally overlying the fieldoxide region 115, without reducing the photosensitive area of the pixelcell, or only partially over the field oxide region 115. Storagecapacitors 399 a, 399 b of pixel sensor cell 300 (FIG. 14) may be alsoformed totally overlying the photosensitive area of the pixel cell, oronly partially over the active area. The processing for the formation ofthe storage capacitors 399 a, 399 b of pixel sensor cell 300 of FIG. 14are similar to the processing steps described above with reference toFIGS. 4-11, except that two capacitors (and not one capacitor) areformed over the field oxide region. In addition, contact 346 (FIG. 14)and contact 347 (FIG. 14) connect each of the lower electrode of thestorage capacitors 399 a, 399 b to the photodiode region 125 or 110 andto the floating diffusion region 130, respectively. Preferably, contacts346, 347 are formed of a conductive material, such as doped polysilicon,or a metal such as titanium/titanium nitride/tungsten. Photolithographictechniques are used to define the areas to be etched out to form theholes for the contacts 346, 347 wherein the conductive material issubsequently depositing therein.

Although FIG. 14 illustrates only two storage capacitors 399 a, 399 b,it must be understood that the present invention is not limited to thisembodiment. Accordingly, the invention contemplates the formation of aplurality of such storage capacitors which are formed entirely or onlypartially over the field oxide region, and which are further connectedto various light sensitive and/or electrical elements of the pixelsensor cell.

FIGS. 15-17 illustrate additional embodiments of the present invention,according to which a storage capacitor is connected not to an AC groundsource, as in the previous embodiments, but rather to a gate of one ofthe four transistors of the 4T cell. For example, FIG. 15 illustratesstorage capacitor 499 formed entirely or partially over the field oxideregion 115, and connected to both the photodiode 125 and to the gatestack 127 of the transfer transistor 128. In another exemplaryembodiment, FIG. 16 depicts storage capacitor 599 formed over the fieldoxide region 115 and also connected to both the floating diffusionregion 130 and to the gate stack 127 of the transfer transistor 128.According to yet another exemplary embodiment, storage capacitor 699 ofFIG. 17 is formed over the field oxide region 115 and is furtherconnected to both the floating diffusion region 130 and to a gate of thereset transistor 132.

In each of the embodiments depicted in FIGS. 15-17, the processing stepsfor the fabrication of the storage capacitors 499, 599 and 699 aresimilar to the processing steps described above with reference to FIGS.4-11, except that the upper electrode of each of the storage capacitors499, 599 and 699 is connected not to a ground potential, as in the firstembodiment, but rather to another element of the CMOS imager, forexample, a gate of one of the four transistors of the pixel sensor cell,as described above.

FIG. 18 illustrates yet another embodiment of the present invention,according to which a storage capacitor 799 is formed over the fieldoxide region 115 as part of a three-transistor (3T) cell and not afour-transistor (4T) cell, as previously described with reference toFIG. 12, for example. The only difference between the structure of FIG.18 and that of FIG. 12 is that the structure of FIG. 12 contains anadditional fourth transistor, that is transfer transistor 128. Thus,storage capacitor 799 of FIG. 18 may be also formed entirely or onlypartially over the field oxide region 115 and connected to thephotodiode 125 and the floating diffusion region 130. The processingsteps for the fabrication of the storage capacitor 799 are similar tothe processing steps described above with reference to FIGS. 4-11,except that the storage capacitor 799 is formed by itself over the fieldoxide region, and not simultaneously with the source follower gate ofthe source follower transistor.

A typical processor based system, which includes a CMOS image sensoraccording to the invention is illustrated generally at 642 in FIG. 19. Aprocessor based system is exemplary of a system having digital circuitswhich could include CMOS image sensors. Without being limiting, such asystem could include a computer system, camera system, scanner, machinevision, vehicle navigation, video phone, surveillance system, auto focussystem, star tracker system, motion detection system, imagestabilization system and data compression system for high-definitiontelevision, all of which can utilize the present invention.

A processor based system, such as a computer system, for examplegenerally comprises a central processing unit (CPU) 644, for example, amicroprocessor, that communicates with an input/output (I/O) device 646over a bus 652. The CMOS image sensor 642 also communicates with thesystem over bus 652. The computer system 600 also includes random accessmemory (RAM) 648, and, in the case of a computer system may includeperipheral devices such as a floppy disk drive 654, and a compact disk(CD) ROM drive 656 or a flash memory card 657 which also communicatewith CPU 644 over the bus 652. It may also be desirable to integrate theprocessor 654, CMOS image sensor 642 and memory 648 on a single IC chip.

The above description and drawings are only to be consideredillustrative of exemplary embodiments, which achieve the features andadvantages of the invention. Modification and substitutions to specificprocess conditions and structures can be made without departing from thespirit and scope of the invention. Accordingly, the invention is not tobe considered as being limited by the foregoing description anddrawings, but is only limited by the scope of the appended claims.

It should be noted again that, although the invention has been describedwith specific reference to CMOS imaging circuits having a photodiode anda floating diffusion region, the invention has broader applicability andmay be used in any CMOS imaging apparatus. The CMOS imaging sensor couldhave a photosensor consisting of a photodiode, a photogate, or aphotoconductor to name just three possibilities. The CMOS imaging sensormay also include additional transistors and/or transistor elements, suchas a global shutter transistor, for example. While the above-describedembodiments illustrate a capacitor in a CMOS imager connecting (i) adiffusion region to an AC ground and (ii) a transistor gate to adiffusion region, the invention is not limited to the above-describedembodiments. Accordingly, the present invention also contemplates acapacitor connecting the gates of two transistors, or a capacitorconnecting a gate to a DC voltage, or a capacitor connecting a gate toan AC voltage, or a capacitor connecting a diffusion region to a DCvoltage, or a capacitor connecting a diffusion region to an AC voltage,or a capacitor connecting two diffusion regions.

Also, although exemplary capacitor structures have been described andillustrated, many variations in capacitor structures could be made.Similarly, the processes described above are only exemplary of many thatcould be used to produce the invention. For example, although theinvention has been described above with reference to the formation ofplanar capacitors, such as storage capacitor 199, for example, theinvention has also application to other capacitor structures, forexample, trench capacitors, stacked capacitors, metal capacitors,container capacitors, HSG capacitors, among others.

Accordingly, the above description and accompanying drawings are onlyillustrative of exemplary embodiments that can achieve the features andadvantages of the present invention. It is not intended that theinvention be a limited to the embodiments shown and described in detailherein. The invention is limited only by the scope of the followingclaims.

1-121. (canceled)
 122. A pixel cell comprising: a field oxide regionformed in a substrate; a doped layer of a first conductivity type formedin said substrate and adjacent said field oxide region; a chargecollection region formed in said doped layer; a first doped region of asecond conductivity type formed in said doped layer adjacent said chargecollection region; and a charge storage capacitor having a firstelectrode connected to said first doped region and a second electrodeconnected to said charge collection region, said charge capacitor beingformed at least partially overlying said field oxide region.
 123. Thepixel cell according to claim 122, wherein said storage capacitor isformed fully overlying said field oxide region.
 124. The pixel cellaccording to claim 122, wherein said storage capacitor is one of atrench capacitor, a stacked capacitor, a metal capacitor, a HSGcapacitor and a container capacitor.
 125. The pixel cell according toclaim 122, wherein said storage capacitor is a flat plate capacitorincluding a dielectric layer between said first and second electrodes.126. The pixel cell according to claim 125, wherein said first andsecond electrodes are independently selected from the group consistingof doped polysilicon, hemispherical grained polysilicon, TiN, poly/WSix,polyTiSi2, and poly/WNx/W.
 127. The pixel cell according to claim 122,further comprising a reset transistor having a gate electricallyconnected to said first doped region.
 128. The pixel cell according toclaim 122, further comprising a source follower transistor having a gateelectrically connected to said first doped region.
 129. The pixel cellaccording to claim 128, further comprising a row select transistorelectrically connected to said source follower transistor to selectivelyoutput a signal from said source follower transistor.
 130. The pixelcell according to claim 122, wherein said first doped region is afloating diffusion region.
 131. A CMOS imager system comprising: (i) aprocessor; and (ii) a CMOS imaging device coupled to said processor,said CMOS imaging device comprising: a pixel cell array, at least onepixel cell of the array comprising: a field oxide region formed in asubstrate; a doped layer of a first conductivity type formed in saidsubstrate and adjacent said field oxide region; a charge collectionregion formed in said doped layer; a first doped region of a secondconductivity type formed in said doped layer adjacent said chargecollection region; and a charge storage capacitor formed at leastpartially overlying said field oxide region.
 132. The system accordingto claim 131, wherein said storage capacitor is electrically anddirectly connected to at least one of said first doped region, saidcharge collection region, and a transistor.
 133. The system according toclaim 131, wherein said storage capacitor is formed fully overlying saidfield oxide region.
 134. The system according to claim 131, wherein saidstorage capacitor is one of a trench capacitor, a stacked capacitor, ametal capacitor, a HSG capacitor, a container capacitor and a flat platecapacitor.
 135. The system according to claim 131, further comprising atransfer transistor for transferring charge accumulated in said chargecollection region to said first doped region, wherein a gate of saidtransfer transistor is formed adjacent said charge collection region.136. The system according to claim 135, wherein an electrode of saidstorage capacitor is electrically connected to the gate of said transfertransistor.
 137. The system according to claim 135, further comprising asource follower transistor for outputting charge accumulated in saidfirst doped region which has been transferred to said first dopedregion, wherein a gate of said source follower transistor is formedadjacent said first doped region.
 138. The system according to claim137, wherein an electrode of said storage capacitor is electricallyconnected to the gate of said source follower transistor.
 139. Thesystem according to claim 131, further comprising a row selecttransistor, wherein a gate of said row select transistor is electricallyconnected to an electrode of said storage capacitor.
 140. The systemaccording to claim 131, further comprising a reset transistor, wherein agate of said reset transistor is electrically connected to an electrodeof said storage capacitor.
 141. The system according to claim 131,further comprising a global shutter transistor, wherein a gate of saidglobal shutter transistor is electrically connected to an electrode ofsaid storage capacitor.